The invention relates to plastic pin grid array (PPGA) packages in which a multilayer printed wiring board (PWB) provided with an array of pins extending from one face thereof. A semiconductor device is attached to the other face and connections are made between the bonding pads of the semiconductor device and metal lands on the PWB which interconnect with the pins. The board is constructed so that metal traces form an array of metal lands, surrounding the semiconductor site, that connect to the pins extending from the opposite face. First, a semiconductor device is mounted on the PWB and connected to the metal lands. Then a plastic housing is transfer molded so as to cover the PWB face holding the semiconductor device and thereby encapsulate it. The plastic encapsulation is described in U.S. Pat. No. 4,688,152 and its divisional process U.S. Pat. No. 4,778,641. The teaching in these two patents is incorporated herein by reference.
The PPGA package has proven to be very useful, in part because a more or less conventional multilayer PWB is employed in its fabrication. The alternative is to use a ceramic multilayer substrate and after the semiconductor device is attached and connected to the ceramic, a plastic or metal cover, of some sort, is applied to provide encapsulation. However, it has been found that the ceramic substrates are subject to relatively high interlead capacitance which seriously reduces the speed of the encapsuated semiconductor devices. Furthermore, such ceramic substrates are expensive thus making their use undesirable.
As shown in the above-referenced patents, the PWB is normally provided with a recess or cavity that accommodates the semiconductor chip. The cavity is typically provided with a metallized bottom to which the semiconductor chip can be soldered or cemented. This metallization is connected to one or more of the array pins so that an external substrate connection is available. The cavity is typically surrounded by an array of metal lands or wiring traces which are also connected, via the multilayer PWB, to the array pins. In assembly the semiconductor device metallization pads are typically interconnected to the metal traces by means of stitch bonded metal wires. Alternatively, a metal spider of the thermal-compression assembly bonding (TAB) type of construction can be employed. The subsequently applied plastic encapsulant covers and protects the semiconductor device and its interconnection means. It also can be extended over the peripheral edges of the PWB to provide a locking skirt which, if desired, can be further extended at the package corners to provide for a package standoff in the final device assembly onto a motherboard.
It is well known that the typical multilayer PWB is flexible to some degree. This dictates that a relatively thick board must be employed so that sufficient rigidity is present and the completed package is not excessively fragile. However, board thickness is a design compromise. After assembly a certain amount of flexure can be encountered. Such flexure can adversely affect the semiconductor device. In an extreme condition the semiconductor device can be fractured. In a lesser flexure condition the connection between the semiconductor device and the PWB can be disrupted. In addition, it is possible that the bond between the plastic encapsulant and the semiconductor surface can be ruptured. In this latter case, the wires that are bonded to the semiconductor device bonding pads can be severed. Accordingly, it would be desirable to provide structural strength for resisting flexure of the PPGA package after assembly.